With the rising level of integration in semiconductor device integrated circuits and with higher device densities, there has been a growing demand for multilayer structures, particularly in semiconductor device elements. This trend toward higher integration results in narrower line spacings, which has led to the problem of wire delay due to increased capacitance between lines {see Japanese Patent No. 3585384 (Paragraph No. 0002)}.
More specifically, although declines in signal propagation speed due to the parasitic capacitance of dielectric films have hitherto been known to occur, in generations of semiconductor devices with line spacings of more than 1 μm, wire delay had only a small effect on the device as a whole. However, at line spacings of 1 μm or less, wire delay has an increased influence on device speed; in particular, when circuits are formed at line spacings of 0.1 μm or less, the parasitic capacitance between lines exerts a large influence on device speed.
The wire delay (T) is affected both by the wiring resistance (R) and the capacitance (C) between lines, as illustrated by formula (8) below.T∝μCR  (8)
The relationship between C in formula (8) and the dielectric constant ∈ is shown in formula (9).C=∈o∈rS/d  (9)
In formula (9), S is the electrode surface area, ∈o is the dielectric constant of a vacuum, ∈r is the dielectric constant of the dielectric film, and d is the line spacing.
Hence, lowering the resistance of the wiring and lowering the dielectric constant of the dielectric film are effective ways to make the wire delay smaller.
Up until now, low dielectric constant dielectric films in semiconductor integrated circuits have been made primarily of silicon compound-based materials, and copper has been used for the metal wiring in the multilayer wiring structures of semiconductor integrated circuits. When a barrier layer is not used in this case, thermal diffusion, etc. of the copper may result in copper infiltration into the silicon compound-based material, possibly causing the insulating properties of the low dielectric constant dielectric film to deteriorate. Hence, deterioration in the insulating properties of a silicon compound-based low dielectric constant dielectric film is currently prevented by forming a barrier film between the copper and the low dielectric constant dielectric film.
Metallic materials are used today in the barrier films of semiconductor integrated circuits (these films are called “barrier metal films”). For example, barrier metal films currently in use have a large thickness of about 10 nm, and are typically made of a metal-based material such as TaN or tantalum which has a large resistance. However, metal-based materials used as the barrier film have a high electrical resistance compared with the wiring metal, and thus increase the line resistance of the semiconductor device as a whole. This is an impediment to high-speed operation and high reliability in semiconductor integrated circuits.